Iris template generation with parallel logic
Ryan N. Rakvic, Bradley J. Ulis, Randy P. Broussard, Robert W. Ives · 2008
Modern iris recognition algorithms can be computationally intensive, yet are designed for traditional sequential processing elements, such as a personal computer. However, a parallel processing alternative using field-programmable gate arrays (FPGAs) offers an opportunity to speed up iris recognition. Within the means of this project, iris template generation with directional filtering, which is a computationally expensive, yet parallel portion of a modern iris recognition algorithm, is parallelized on an FPGA system. We will present a performance comparison of the parallelized algorithm on the FPGA system to a traditional CPU-based version. The parallelized template generation outperforms an optimized C++ code version determining the information content of an iris approximately 324 times faster.