An optimisation communication cost algorithm for dynamically reconfigurable FPGAs
Chi‐Chou Kao, Tzu-Chiang Tai, Yen‐Tai Lai · International Journal of Electronics · 2010
In this article, we present a sequential circuit partitioning algorithm to optimise the number of registers for dynamically reconfigurable FPGAs. The algorithm is divided into two phases: (1) the labelling phase and (2) the minimising cost phase. We first improved the ‘as soon as possible’ and ‘as late as possible’ algorithms to assign nodes so that the constraints of partition a sequential circuit partition are satisfied for dynamically reconfigurable FPGAs. Then, some nodes are adjusted or replicated to optimise the number of registers. Experimental results demonstrate the effectives of our algorithms.