The research on optimization techniques of 32-bit floating-point RISC microprocessor
Sun Haijun, Shao Zhibiao, Zom Gang, Zhao Ning · 2005
A high-performance low power dissipation 32-bit floating point RISC microprocessor XJ-1 has been successfully fabricated in 0.35 /spl mu/m CMOS technology. A set of innovative optimization techniques are introduced for high performance operation, which include modified redundant Booth-3 algorithm for fast multiplication or division, dynamic SRAM mode control scheme for low power dissipation, embedded bus preselector improving the performance of bus interface, and the large capacity on-chip memory decreasing the amount of traffic with an external memory. These techniques improved the speed and quality with 38% boosted frequency and 39% reduced power dissipation. Each instruction and its random combinations have been tested, and the chip achieves 0.98 mA/MHz at 3.3 V power supply.