Efficient BIST TPG design and test set compaction for delay testing via input reduction
C.-A. Chen, Sandeep K. Gupta · 2002
This paper describes an input reduction design framework for delay testing. This design framework can be used to construct efficient test pattern generators (TPGs) for built-in self-test (BIST), to order scan cells in a scan chain to eliminate unnecessary dummy flip-flops, and to generate compact test sets for delay testing.