Formal Methods and VLSI Engineering Practice
Victoria Stavridou · The Computer Journal · 1994
This paper surveys the state of the art in the use of formal verification for hardware design and discusses the transfer of such methods to industrial practice. We examine the characteristics of the VLSI engineering process and propose a set of criteria for evaluating the applicability of various formal approaches to the design of digital systems. We also discuss some topics for future research to enable effective technology transfer of formal methods to VLSI engineering practice