Data path allocation for synthesizing RTL design with low BIST area overhead
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer · 1995
Article Data path allocation for synthesizing RTL design with low BIST area overhead Share on Authors: Ishwar Parulkar Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CAView Profile , Sandeep Gupta Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CAView Profile , Melvin A. Breuer Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CAView Profile Authors Info & Claims DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation ConferenceJanuary 1995 Pages 395–401https://doi.org/10.1145/217474.217561Online:01 January 1995Publication History 37citation177DownloadsMetricsTotal Citations37Total Downloads177Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access