RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults
Abhijit Chatterjee, Jacob A. Abraham · 1994
of low voltage testing for the detection of weak CMOS logic The problem of delay fault-testing and detection of chips with marginal performance has become even more critical than before due to advancing clock speeds. In this paper, a methodology for detection of marginal digital circuits and diagnosis of gate delay failures is developed. A new test appli-cation methodology is proposed in which test vectors may be applied to digital combinational circuits at intervals smaller than the critical path delay of the circuit and signal waveform analysis is used to interpret the test results. The resulting tests ICs. Most relevant to the research presented in this paper is the work of Franco and McCluskey 16. They have suggested output signal waveform analysis using time-domain integration as a means of analyzing circuit response to delay tests. We use a similar signal waveform analysis approach in this paper. Our research complements their earlier work by investigation of the test generation problem, the use of rapid-fire tests, the ability to identify marginal chips and the ability to perform fault diagnosis. are called RApid Fire Tests (for RAFT) and allow classification of circuits from "good " to "bad " along a continu-2. Problem Specification ous scale. The problem addressed in this paper is based on the following objectives: 1.