A high-speed pipeline processor for regional labelling based on a new algorithm
Tetsuo Hattori · 2002
A high-speed regional labeling processor which continuously processes images from an image area sensor at the NTSC video rate, i.e., at the speed of 30 images (512*512*8 b/frame)/s is presented. An algorithm implemented in the processor is described. Since this algorithm retains the label's linkage information in the form of simple linear list structure and not in graph structure, the hardware of the processor is very simple and has been implemented by wired logic alone.>