Low Power Embedded Deterministic Test
Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer · Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium · 2007
This paper presents a novel low power test scheme integrated with the embedded deterministic test environment. It reduces switching rates in scan chains with no hardware modification. Experimental results obtained for industrial circuits indicate that switching activity can be reduced up to 23 times.