On-line arithmetic-based reprogrammable hardware implementation of multilayer perceptron back-propagation
Bernard Girau, Arnaud Tisserand · 2002
A digital hardware implementation of a whole neural network learning is described. It uses on-line arithmetic on FPGAs. The modularity of our solution avoids the development problems that occur with more usual hardware circuits. A precise analysis of the computations required by the back-propagation algorithm allows us to maximize the parallism of our implementation.