A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications
Chang-Hyo Yu, Kyu-Sik Chung, Donghyun Kim, Lee‐Sup Kim · 2006
A 3D vertex processor with a floating-point 4-threaded and 4-issue VLIW architecture and a TnL vertex cache is implemented for mobile multimedia applications in a 0.18μm 4M CMOS process. The proposed architecture efficiently reduces the total energy consumption and achieves 120Mvertices/s with a 2.5GFLOPS datapath using 157mW when operating at 100MHz