An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration
Andrei Rădulescu, J. Dielissen, Kees G. W. Goossens, E. Rijpkema, Paul Wielage · 2004
In this paper we present a network interface for an on-chip network. Our network interface decouples computation from communication by offering a shared-memory abstraction, which is independent of the network implementation. We use a transaction-based protocol to achieve backward compatibility with existing bus protocols such as AXI, OCP and DTL Our network interface has a modular architecture, which allows flexible instantiation. It provides both guaranteed and best-effort services via connections. These are configured via network interface ports using the network itself, instead of a separate control interconnect. An example instance of this network interface with 4 ports has an area of 0.143mm2 in a 0.123µm technology, and runs at 500 MHz.