A high throughput architecture for channel equalization based on a neural network using a wave pipeline method
François Morin, M. Vidal, Daniel Massicotte · 2003
The use of a wave pipelining method for the design of a systolic architecture dedicated to channel equalization is proposed. A description is given of the piecewise linear multilayer neural network (PL-MNN) algorithm and the architecture. To improve the throughput of the architecture we propose a wave-pipelined version of the multiplier-accumulator (MAC) the presents the bottleneck of the architecture. A 16/spl times/8-bit MAC is performed using a normal process complementary pass transistor (NPCPL) as a universal cell for the creation of conventional logic gates and is used to optimize the wave pipelined MAC. The throughput and the latency of the MAC have been evaluated at 650 MHz and 8 ns respectively. The performance has been evaluated in a 0.5 /spl mu/m CMOS technology in comparison with the systolic architecture with and without a conventional pipeline and the proposed wave pipeline structure.