Design Parallel Direct Digital Frequency Synthesizer Using Interpolation and QLA Technology
Zhao Xin, Qi Jun, Bihai Tu, Yi Zhang, Cheng Jie-xiang, Jianguo Liu, Zhao Pin-jian · 2006
A novel direct digital synthesis (DDFS) architecture is presented in this paper and achieved by FPGA. It consists of a phase accumulator, four phase-to-sine converters and off-chip D/A converter. The phase accumulator use pipelined parallel architecture; it consumes only 22% power of conventional pipelined accumulator with the same throughput. The interpolation and quad line approximation (QLA) minimize the phase-to-sine module to generate a sine waveform. The QLA saves 4 bits of the sine amplitude by approximating the sine function with four lines. The interpolation method splits the phase-to-sine module into coarse ROM and fine ROM; it stores quantized values and the quantized errors separately. The Rom size for 12-bits sine output is only 36 Kbits, the compressed ratio is 78.2:1. It consumes only 170 mW with 3.3 V in FPGA, the spurious-free dynamic range (SFDR) is 63 dBc