SADE: a graphical tool for VHDL-based system analysis
Jukka Lahti, Matti Sipola, Jorma Kivelä · 2002
A graphical tool for system analysis called SADE (System's Analyst's Design Environment) is described. The tool can generate behavioral VHDL (VHSIC Hardware Description Language) models from graphical, structured analysis diagrams. The models can be simulated on a standard VHDL simulator. The simulation results can be viewed animated in the graphical diagrams. The tool provides the designer with features found in sophisticated CASE tools, which make the construction of a system model and the analysis of simulation results easy.>