A VLSI design of a pipeline FFT in GF(256)
Jinxiang Wang, Mao Zhigang, Yizheng Ye · 2002
A pipeline VLSI design of FFT based on Good-Thomas algorithm is presented, to implement FFT with 255 points in GF(256), this design only needs 60 eight bits galois multipliers, a ROM to store 30 twiddles and some registers. The latency is 255+17 clock cycles, and the maximum combination delay is the sum of one multiplier in GF(256) and four stage XOR gates. This design is modular, regular, simple and suitable for VLSI implementation.