Design for testability of an asynchronous adder
O.A. Petlin · 1996
Modern technological processes for producing VLSI circuits have created an opportunity to exploit the advan-tages of asynchronous circuits. Compared to their synchronous counterparts, asynchronous circuits have the potential for lower power consumption, offer greater design flexibility, exhibit average rather than worst-case performance and have no problem with clock skew [Lav93, Hauck95]. Asynchronous circuits can be divided