1993 International Conference on Parallel Processing SPACE - TIME REPRESENTATION OF ITERATIVE ALGORITHMS AND THE DESIGN OF REGULAR PROCESSOR ARRAYS
E. D. Kyriakis, Odysseas Koufopavlou, C.E. Goutis · 1993
A tie wl space-rirt~e reprexetrra~ids oj' itemf ive nlgorill~nrs, which ccrrri be expresscl it; t~ei~e~i loop form atld )tray irrclude noti-cc)tlsmtlr depencler~cics is propos~d arid arys~etmric ~rrert~dology for their nlcrppirrg otrro regular processor arrqs is present&. I11 cot~rrflr.t rcr previous design merhodolog ies, rl~r esecuriot; t it11lc of RII~ variable insmnce is arplici~ly expressed it1 the Depetiderice Graph, by rloe corjsrrucriotr of the Space- Time Depetjderice Grnph (SlDG). nlis nppronch avoids he uriforrrrizntioti step of rhe olgorirhni atid the requiremetlr for fly itulaitlg /he vnrinbles. ALSO, itr the STDG dependence wcrors hnvitig opposire clirecriotls do tlor exist atd therefore, a litrear ni~ppirrg oflhe S7DG or~ro the processor array cntr nl ways be derived. Eflcie~jt 2-0 nttd I-D regular processor nrrclys clre produced by npplyittg the merhod to the Wnrshnll-Floyd nlgorirhtr~.