A General Purpose, Highly Efficient Communication Controller Architecture for Hardware Acceleration Platforms
Petersen F. Curt, James P. Durbano, Fernando E. Ortiz, John R. Humphrey, Dennis W. Prather · 2005
Although researchers have presented individual techniques to efficiently utilize the peripheral component interconnect (PCI) bus, their contributions fail to provide a direct path to large communication bandwidth for FPGA-based hardware accelerators. Because of the increasing use of FPGAs as application accelerators, there is a need for another, more powerful communication layer to sustain very large data transfers. This paper presents the implementation of such an infrastructure and provides the designer with a familiar, easy-to-use interface. When incorporated into existing designs, 30-fold speed improvements over off-the-shelf PCI cores from Xilinx have been demonstrated.