HARDWARE REDUCTION IN FPGA-BASED MOORE FSM
Alexander A. Barkalov, Larysa Titarenko, Raisa Malcheva, К. А. Солдатов · Journal of Circuits Systems and Computers · 2013
The methods are proposed targeting to reduce the numbers of both look-up table elements and embedded memory blocks in the logic circuit of a Moore finite state machine. The proposed methods are based on binary encoding of both classes of pseudoequivalent states and collections of microoperations. Examples of synthesis and results of investigations are given.