A CAD Tool for Scalable, Variable Architecture Floating-Point Adder Generator
Asim J. Al-Khalili · IEEE International Conference on Computer Systems and Applications, 2006. · 2006
New low power architecture for floating point adders is presented. The method is further enhanced by the introduction of pipelining. These two architectures together with the standard Floating Point Adder form the basis for development of a CAD tool for generating VHDL codes for Scalable Floating Point adders. The user interface is designed using C++ to give the user the choice of different Floating Point Adders (FADD) and the adding precision. The CAD tool then selects the appropriate FADD and generates a synthesizable VHDL code, corresponding to the selected FADD and the precision values entered by the user. Thus an architecture corresponding to a low delay or low power or low area can be selected. The architectures conform to IEEE 754 standard.