3-dimensional systolic architecture for parallel VLSI implementation of the discrete cosine transform
S. S. Nayak, Pramod Kumar Meher · IEE Proceedings - Circuits Devices and Systems · 1996
Two different linear systolic arrays have been suggested for the computation of discrete cosine transform (DCT). The proposed linear arrays are complementary to each other in the sense that the output of the linear arrays of one type may be fed as the input for the linear arrays of the other type. This feature of the proposed linear arrays has been utilised for designing a bilayer structure for computing the prime-factor DCT. It is interesting to note that the proposed structure does not require any hardware/time for transposition of the intermediate results. The desired transposition is achieved by orthogonal alignment of the linear arrays of the upper layer with respect to those of the lower layer. The proposed structures provide high throughput of computation due to fully pipelined processing, and massive parallelism employed in the bilayer architecture.