Increase the behavioral fault model accuracy using high-level synthesis information
Marco Brera, Fabrizio Ferrandi, Donatella Sciuto, Franco Fummi · 2003
This paper describes an approach for enhancing the effectiveness of behavioral test generation by considering high-level and logic synthesis information to increase the correlation between the behavioral fault model and the stuck-at-fault model. In particular we mainly consider two types of information: the mapping between high-level operators and RTL modules and the type of gate level implementation adopted by the RTL modules.