Constraint synthesis for environment modeling in functional verification
Jun Tang Yuan, Ken Albin, Adnan Aziz, Carl Pixley · 2003
Modeling design environment with constraints instead of a traditional testbench is advantageous in a hybrid verification framework that encompasses simulation and formal verifica-tion. This movement is gaining popularity in industry and sparks research in the constraint-based environment mod-eling and stimulus generation problem. We present an ap-proach, called constraint synthesis, to this problem. Con-straint synthesis falls in the general category of parametric Boolean equation solving but is novel in utilizing don’t care information unique to hardware constraints and heuristic variable removal to simplify the solution. Experimental re-sults have demonstrated the effectiveness of the proposed approach.