Scalable matrix multiplication algorithm for IRAM architecture machine
G. Vesztergombi, Géza Ódor, F. Rohrbach, G. Varga · 2002
A scalable bit matrix machine model was proposed by us previously (G. Vesztergombi et al., 1997). Now we extend this IRAM type model for numerical calculations. The k digit numbers are represented in a bit parallel way, thus the number of rows in the memory is scaled up correspondingly, which means that the number of 1 bit CPUs is also increased proportionally. Still relying on the simple string communication interprocessor network, we prove that loading and multiplication of n/spl times/n matrices are executable in O(n) time. Speed estimates are calculated using emulation on the 8192 processor CERN-ASTRA machine.