VLSI implementation of a neural network classifier
R.L.K. Mandisodza, Dennis Lüke, Przemyslaw Pocheć · 2002
Design and implementation of a neural network classifier is discussed. The classifier is based on the 25 node Hopfield network design. The proposed implementation is on a Xilinx(R) XC4000 FPGA family chip. The design methodology and the resource usage are discussed. An example application of the classifier in pattern recognition is presented.