At-Speed Current Testing *
Yinghua Min, Jishun Kuang, Xiaoyan Niu · Asian Test Symposium · 2003
This paper proposes a scheme of at-speed current testing by applying two alternative vectors to circuits under test for a fault to enable a slow measurement under a high frequency operation. The paper presents test generation of the two alternative vectors at gate level by means of counting only logical up-transitions based on Boolean process, and employing the Bayesian optimization algorithm. SPICE simulation shows that the responses of tests generated by the algorithm can be observed either by a low-cost ATE or a waveform sensor. Index Terms—current testing, logical transition, hazard, stuck-open fault