High-speed HEC algorithm for ATM
Chung-Wook Suh, Kyung-Soo Kim · 2002
A high-speed HEC (header error control) algorithm for the 16-bit mode of ATM (asynchronous transfer mode) interface system is presented. Thanks to using the property of the Galois field and the parallelism of the linear feedback shift register, this algorithm is very efficient and simple in accomplishing the more than 622 Mbps of cell transmission. Through implementing in VHDL (very-high-speed-integrated-circuit hardware description language), the comparison of the proposed algorithm with the byte-mode algorithm shows that the proposed algorithm has lower latency, higher throughput and less hardware complexity than the latter.