Queue structure and optimal buffer division between ingress/egress ports in crossbar-based switches
Qi Cao, Chin‐Tau Lea, An Chen · 2005
The memory used in high-speed switching often needs to be customer designed and is expensive. As the link speed approaches 10-G and 40-G rates, reducing the memory requirement can translate into significant cost saving. In this paper, we study an optimal memory partition scheme between ingress ports and egress ports of a crossbar-based switch. We show how the optimal partition between ingress and egress ports can save memory, and how the partition is affected by the queue structure in the switch. Compared with the 50-50 partition, the optimal partition scheme can reduce buffer requirements by at least 30%.