A method for testing partially programmable logic arrays in CPLDs
J. Bailey, Charles E. Stroud, N.J. Vocke, N. Lau, W.R. Orso, Canh Quang Tran · 2002
We describe a method for developing a minimal set of four test configurations with associated minimum sets of test patterns that completely tests reprogrammable Programmable Logic Arrays (PLAs) with partially programmable OR-planes typically found in Complex Programmable Logic Devices (CPLDs). The resultant set of test configurations and vectors detect all single and multiple stuck-at faults (including line and transistor faults) as well as all bridging faults without requiring hardware modifications in the PLA. Previous methods for testing reprogrammable PLAs have dealt only with fully programmable OR-planes.