A High-Level Synthesis Approach to Optimum Design of Self-Checking Circuits
Anna Antola, Vincenzo Piuri, Mariagiovanna Sami · 1996
We present an innovative solution to design of selfchecking systems implementing arithmetic algorithms. Rather than substituting self-checking units in system synthesized independently of self-checking requirements, we introduce self-checking in high-level synthesis as a requirement already for scheduling the DFG. Rules granting error detection allow optimum partitioning of the DFG; minimum-latency, resource-constrained scheduling is performed with the support of such partitioning so as to optimize the number of checkers as well as that of other resources.