A built-in I/sub DDQ/ test circuit utilizing upper and lower limits
Yoshio Miura, Sachio Naito · 2002
A test circuit for the built-in I/sub DDQ/ testing is proposed. The circuit can use two current values, an upper limit and a lower limit, to judge whether CUT is fault-free or not. The test circuit is applicable to fault detection for both digital and analog circuits. We show the efficiency of the test circuit using SPICE3 simulator.>