Test vector generation for charge sharing failures in dynamic logic
Keerthi Heragu, M. Sharma, Ritankar Kundu, Ronald DeShawn Blanton · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2002
Dynamic logic is increasingly becoming a logic type of choice for designs requiring high speed and low area. Charge sharing is one of many problems that may cause failure in dynamic logic circuits due to their low noise immunity. The authors address the charge-sharing noise issue. Specifically, they develop an accurate but tractable model for analyzing charge sharing that avoids costly Hspice simulations. The model is used to generate test vectors using a generalized ATPG tool. The charge-sharing model and the corresponding tests are validated using Hspice simulations on industrial circuits and it is also demonstrated that test vectors that establish high amounts of charge sharing could be generated for most domino gates.