Architecture and design of the MARS hardware accelerator
Rahul Agrawal, William J. Dally, A. K. Ezzat, W.C. Fischer, H. V. Jagadish, A. S. Krishnakumar · 1987
MARS (Microprogrammable Accelerator for Rapid Simulations) is a multiprocessor based hardware accelerator capable of efficiently implementing a wide range of computationally complex algorithms. Its architecture is ideally suited for performing event driven simulations of VLSI circuits. The highly pipelined and parallel architecture of MARS provides a performance comparable to existing hardware simulation engines while its highly flexible architecture supports a wide range of applications. Flexibility is achieved through custom designed microprogrammable and reconfigurable VLSI processors. Logic simulation performance of about one million events per second is easily achievable.