Design of Vector Register Architecture in DSP Processor for Efficient Multimedia Processing
Chou-Pin Wu, Jen‐Ming Wu · JSTS Journal of Semiconductor Technology and Science · 2007
In this paper, we present an efficient instruction set architecture using vector register file hardware to accelerate operation of general matrixvector operations in DSP microprocessor. The technique enables in-situ row-access as well as column access to the register files. It can reduce the number of memory access significantly. The technique is especially useful for block-based video signal processing kernels such as FFT/IFFT, DCT/IDCT, and two-dimensional filtering. We have applied the new instruction set architecture to in-loop deblocking filter processing in H.264 decoder. Performance comparisons show that the required load/store operations for the in-loop deblocking filter can be reduced about 42%. The architecture would improve the processing speed, and code density in DSP microprocessor especially for video signal processing substantially.