Customizing 16-bit floating point instructions on a NIOS II processor for FPGA image and media processing
Daniel Etiemble, Samir Bouaziz, Lionel Lacassagne · 2005
We have implemented customized SIMD 16-bit floating point instructions on a NIOS II processor. On several image processing and media benchmarks for which the accuracy and dynamic range of this format is sufficient, a speed-up ranging from 1.5 to more than 2 is obtained versus the integer implementation. The hardware overhead remains limited and is compatible with the capacities of today's FPGAs.