Computing in 3D
Paul D. Franzon, Eric Rotenberg, William Rhett Davis, James M. Tuck, William Rhett Davis, Huiyang Zhou, Joshua Schabel, Zhenquian Zhang, J. Brandon Dwiel, Elliott Forbes, Joonmoo Huh, Marcus Tshibangu, Steve Lipa · 2015
3DIC technology refers to stacking and interconnecting chips and substrates (“interposers”) with Through Silicon Vias (TSVs). Industry is gearing up for widespread introduction of this technology with the 22 nm node. We have been pursuing a range of approaches to enable low power computing. As well as 3DIC these include heterogeneous computing, powered optimized SIMD units, optimized memory hierarchies, and MPI with post-silicon customized interconnect. Heterogeneous computing refers to the concept of building a mix of CPUs and memories that in turn enable in-situ tuning of the compute load to the compute resources. We introduce the concept of Fast Thread Migration using 3DIC technologies. We present the design of a power optimized SIMD unit in which over half of the power is employed in the FP units. A parallel computer is built using an MPI paradigm. Codes are analyzed so that the MPI interconnect can be power optimized post-silicon. Emerging 3D memories have potential to be employed as Level 2 and Level 3 caches, and this is explored using the Tezzaron 3D memory. As scaling and power optimization occurs, the main memory increasingly dominates the power consumption. Possible extensions to Cortical Processing are discussed.