FPGA interconnect testing algorithm based on routing-resource graph
Li Dai, Zhi-bin Liu, Shao-chi Liang, Meng Yang, Lingli Wang · 2008
Static-random-access-memory(SRAM)-based field programmable gate arrays (FPGAs) consists of 50% ~70% routing resources. A simple programmable interconnect point (PIP) is a switch controlled by SRAM configuration cell connecting two wires. A novel traverse algorithm targeted for the detection of PIP open faults is proposed. Experimental results run on the Fudan design system (FDS) platform show that the algorithm is effective to examine the open faults of the routing paths caused by the PIPs fault configuration.