FlexGrip™: A small and high-performance programmable hardware for highly sequential application
Takashi Yoshikawa, Fumihiko Hyuga, Masayuki Tokunaga, Yutaka YAMADA, Shigehiro Asano · 2011
Although the state-of-the-art multi-core/many-core processors with SIMD extension are getting powerful enough for full software implementation of highly data-parallel application, highly sequential application still requires dedicated hardware for accelerating its performance because it lacks data-parallelism. In this paper, we propose a novel programmable hardware called FlexGrip™, which aims at software implementation of Context-Adaptive Binary Arithmetic Coder (CABAC) without dedicated hardware. Our evaluation result shows that gate count of FlexGrip is about 359K gates per core, and with two FlexGrips CABAC is decoded at about 50Mbps and about 120mW is consumed if operated at 333MHz.