A single chip, 5 GOPS, macroblock-level pixel processor for MPEG2 real-time encoding
S. Nakagawa, K. Kawamoto, T. Yamanaka, Hideo Ohkuma, Y. Habara, S. Masuda, Hiroshi Nakagawa, Koichi Nishigaki, Katsumichi Ishida, Atsushi Maeda, Masahiko Yoshimoto · 2002
A single chip, ITU-R-601 resolution pixel processing LSI for MPEG2 real-time encoding has been developed. The chip attains 5 GOPS pixel processing performance using a hybrid scheme which is supported by hardwired processing units and a programmable RISC unit. The RISC unit realizes user-defined adaptive algorithms in the encoding process. Furthermore an on-chip programmable timing scheduling unit provides the flexibility of the macroblock-level data flow control. A unique port configuration eliminates data transfer bottlenecks to ensure enough high throughput rate for MPEG2 pixel processing. The chip was fabricated in 0.5 /spl mu/m CMOS double metal technology with 14.54/spl times/14.89 mm/sup 2/ die area. It operates at 100 MHz and consumes 3.5 W at 81 MHz.