Efficient techniques for reducing error latency in on-line periodic built-in self-test
Hussain Al-Asaad · IEEE Instrumentation & Measurement Magazine · 2010
Due to the high cost of failure, verification and testing now account for more than half of the total lifetime cost of an integrated circuit (IC). Increasing emphasis needs to be placed on finding design errors and physical faults as early as possible in the life of a digital system, new algorithms need to be devised to create tests for logic circuits, and more attention should be paid to synthesis for test and on-line testing. On-line testing requires embedding logic that continuously checks the system for correct operation. Built-in self-test (BIST) is a technique that modifies the IC by embedding test mechanisms directly into it. BIST is often used to detect faults before the system is shipped and is potentially a very efficient way to implement on-line testing. Error latency is the elapsed time between the activation of an error and its detection. Reducing the error latency is often considered a primary goal in on-line testing.