A 1.2 GFLOPS neural network chip for high-speed neural network servers
Y. Kondo, Y. Koshiba, Yutaka Arima, M. Murasaki, TAIJI YAMADA, H. Amishiro, Haruki Mori, Kazuo Kyuma · IEEE Journal of Solid-State Circuits · 1996
This paper describes a digital neural network chip for high-speed neural network servers. The chip employs single-instruction multiple-data stream (SIMD) architecture consisting of 12 floating-point processing units, a control unit, and a nonlinear function unit. At a 50 MHz clock frequency, the chip achieves a peak speed performance of 1.2 GFLOPS using 24-bit floating-point representation. Two schemes of expanding the network size enable neural tasks requiring over 1 million synapses to be executed. The average speed performances of typical neural network models are also discussed.