A 336-kbit content addressable memory for highly parallel image processing
T. Ogura, M. Nakanishi, Tetsuya Baba, Yasusi Nakabayashi, Ryota Kasai · 2002
This paper describes a 336-kbit (4 kwords/spl times/84 bits) Content Addressable Memory (CAM) LSI with dedicated functions for highly parallel image processing. This LSI can operate as a SIMD PE array, and is a key component of a CAM-based system, HiPIC (Highly-parallel Integrated Circuits and System). New hit-flag generation and multiple-response-resolution schemes are also incorporated in this LSI. A total of 4.2 million transistors are integrated using 0.5 /spl mu/m CMOS process technology. The CAM LSI and HiPIC concept described here will make a significant contribution to the development of real-time image processing systems.