A Low-Latency Asynchronous Shift Register
R.P.-K. Chan, Oliver C. S. Choy, C.-F. Chan, Kong‐Pang Pun · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 2004
In this paper, we first introduce a straightforward asynchronous shift register design implemented by differential cascode voltage switch logic and micropipeline. The corresponding latency defect between data readout is then described. To solve this problem, we propose a new architecture for the design. Finally, a basic building block with respect to our architecture is proposed.