A reuse scenario for the VHDL-based hardware design flow
Viktor Preis, Renate Henftling, Markus Schütz, Sabine März-Rössel · European Design Automation Conference · 1995
We present a reuse scenario for the VHDL-based hardware design flow based on a library of extremely flexible parameterizable components supplemented by the support of most of the phases of the design process ranging from specification refinement and modeling, over simulation and synthesis, down to gate-level verification and HW test support. This reuse scenario has been inspired by the abstraction and modeling capabilities of VHDL and can be best characterized as know-how reuse. Currently, our scenario provides reuse for components with a complexity ranging from 0.1 K to 15 K gates. Qualitative and quantitative results demonstrate the potential and the feasibility of our reuse scenario.