Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods
David John Walter, Scott Little, Chris J. Myers, Nicholas Seegmiller, Tomohiro Yoneda · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2008
This paper presents two symbolic model checking algorithms for the verification of analog/mixed-signal circuits. The first model checker utilizes binary decision diagrams while the second is a bounded model checker that uses a satisfiability modulo theory solver. Both methods have been implemented, and preliminary results are promising.