A reconfigurable processor architecture for high-speed multidimensional digital filtering
S.-M. Park, W.E. Alexander · 2002
A reconfigurable multiprocessor architecture for high-speed 2-D or 3-D digital filtering is presented. The architecture is based upon a computational structure obtained from a state space model. The computational structure is very regular and modular. Thus, it can easily be mapped into a specific arithmetic unit. A processor based on this architecture which uses multiple arithmetic units arranged in parallel fashion and therefore achieves a very high throughput is presented. The processor uses state variable registers which can be configured for both 2-D and 3-D filters. This permits the same arithmetic units to be used for both cases. The processor can be implemented in a single chip using VLSI technology.>