A vector multiply-accumulate architecture for GF(2/sup m/)
M.O. Sanu, Earl E. Swartzlander · 2005
Finite field arithmetic is useful in the implementation of error-correcting codes as well as cryptographic protocols. Large finite field numbers are particularly important in the implementation of elliptic curve cryptography. This paper presents a vector multiply-accumulate (MAC) architecture over the binary extension field GF(2/sup m/) capable of supporting multiple precisions simultaneously. The vector MAC can perform one GF(2/sup m/) or two GF(2/sup m/) multiply-accumulates using essentially the same hardware as a scalar GF(2/sup m/) Mastrovito-type multiplier. The vector capability is enabled by inserting mode-dependent masks in the bit product and reduction arrays of the GF(2/sup m/) MAC. This architecture leverages an existing scalar structure for performing multiple operations in vector mode. Essentially the same hardware is shared between scalar and vector modes. Although there is a slight delay and area penalty for the mode-dependent masking, this overhead is relatively insignificant. We implemented both the stand-alone scalar GF(2/sup m/) MAC and the vector GF(2/sup m/) MAC in structural Verilog and synthesized the designs on a 0.18 micron standard cell library to compare the area and delay for different values of m. The vector MAC can be utilized in an environment where repeated GF(2/sup m/) multiplications that have no dependencies need to be performed. Instead of serializing these individual operations, they can be performed in pairs.