Parallel VLSI computing array implementation for signal subspace updating algorithm
H.A. Abdallah, Yu Hen Hu · IEEE Transactions on Acoustics Speech and Signal Processing · 1989
The parallel VLSI computing array implementation is discussed for novel signal subspace iteration algorithm (SSIA) proposed by I. Karasalo (1986). By making use of a sparse structure, a linearly connected VLSI computing structure is developed for the singular valve decomposition operation used in this algorithm. It is first shown that by making use of a sparse structure matrix the computing time of this algorithm for a single processor can be reduced from O(N/sup 3/) to O(N/sup 2/), where N is the dimensional of the signal subspace. Then it is shown that the parallel architecture can reduce the overall computing time for single-valued decomposition from O(N/sup 2/) to O(N)using O(N) processors. This reduces the total computing time of SSIA from max (O(K/sup 2/), O(N/sup 2/K)) with a single processor to O(K) with O(N/sup 2/) processors, where K is the dimension of the covariance matrix.>