A 500 MHz 1-stage 32 bit ALU with self-running test circuit
Takeshi Yoshida, G. Matsubara, S. Yoshioka, Haruyuki Tago, S. Suzuki, Noriaki Goto · 2002
A 500 MHz 1-stage 32 bit ALU has been designed and fabricated using 0.3 /spl mu/m CMOS process. Main features are a 1.56 ns DPL (Double path-transistor logic) adder and a compact barrel shifter using a newly developed 4-input MUX scheme. A BIST (built-in self test) circuit enables 500 MHz real-time testing. The chip size is 1 mm/spl times/0.38 mm.